TASK3.1: Construct dynamic circuits¶
- Which construct is used to express classical feedforward control within a circuit?
a. QuantumCircuit.if_test used as a context manager
b. QuantumCircuit.if_else with nested with blocks
c. QuantumCircuit.condition decorator on gates
d. QuantumCircuit.classical_control function
answer
The answer is a.
QuantumCircuit.if_test is the supported construct to express conditional execution (classical feedforward) in dynamic circuits. It is used as a context manager within a with statement. Qiskit Runtime currently supports only the conditional if control-flow structure from OpenQASM 3; other higher-level helpers such as a generic if_else or decorators are not available as described in this guide.
- What is the effect of the example circuit that applies
h(q0), measuresq0intoc0, and then appliesx(q0)only ifc0 == 1, followed by a final measurement ofq0?
a. The final outcome is always 0 with near 100% probability
b. The final outcome is 1 with near 100% probability
c. The final distribution remains 50/50 between 0 and 1
d. The result is hardware-dependent and undefined in ideal simulation
answer
The answer is a.
The Hadamard creates an equal superposition; measuring collapses to 0 or 1. If the outcome is 1, the conditional X flips the qubit back to |0⟩. Therefore, after the feedforward correction, the final measurement of q0 yields 0 with essentially 100% probability in the ideal model.
- How do you create an
elseblock paired with anif_testblock?
a. Chain another with circuit.if_test((c, 0)): immediately after
b. Capture the context manager as a target in with circuit.if_test(...) as else_: and then use with else_: for the else block
c. Use with circuit.else_test(): right after the if block
d. Define an else: statement in regular Python (outside the circuit) to emit circuit ops
answer
The answer is b.
if_test returns a context manager that can be assigned (e.g., as else_). This handle can be re-entered with with else_: to add the else branch.
- When conditioning on multiple classical bits (a classical register), which statement is correct?
a. You can condition only on single bits; registers are unsupported
b. You can condition on a register value, using an integer mask like 0b001
c. You must first convert registers to integers with to_int()
d. You must use OpenQASM 3 input files; Qiskit SDK cannot build such circuits
answer
The answer is b.
The guide shows conditioning on the value of a classical register using integer literals (e.g., 0b001). The drawer indicates white/black circles for conditioning on 0/1 for the respective classical bits.
- Which of the following is not allowed according to the listed Qiskit Runtime limitations?
a. Nested if_test blocks (an if_test inside another if_test)
b. Using a single-bit slice from a large classical register in the condition
c. Broadcasting at most 60 bits per broadcast
d. Conditioning on a ≤32-bit-wide classical register
answer
The answer is a.
Nested conditionals are not allowed. The guide explicitly states that an if_test within another if_test is invalid. The other options are supported within stated limits: single-bit conditions from a large register are fine, broadcasts must be ≤60 bits at a time, and register operands must be ≤32 bits when used as the condition.
- The term broadcast in Qiskit Runtime dynamic circuits best refers to which scenario?
a. The number of qubits measured per circuit
b. A transfer of unique classical data for evaluating an if_test condition
c. An emission of results back to the client at the end of execution
d. The total number of measure instructions in the job
answer
The answer is b.
A broadcast is a transfer of unique classical data (bits) required to evaluate if_test conditions. Multiple if_test statements on the same unchanged classical data constitute one broadcast; using a different classical register (or bits) triggers another broadcast.
- Which limit combination is correctly described for Qiskit Runtime?
a. Operand to if_test must be ≤64 bits; broadcasts can be up to 64 bits
b. Operand to if_test must be ≤32 bits; broadcasts can be up to 60 bits
c. No limit on operand width if using OpenQASM 3; broadcasts up to 60 bits
d. Operand to if_test must be ≤16 bits; broadcasts can be up to 32 bits
answer
The answer is b.
The guide states that if_test operands must be 32 bits or fewer and that no more than 60 bits can be broadcast at a time.
- Which of the following is disallowed inside an
if_testblock under current limitations?
a. Applying standard quantum gates like x, h, cx
b. Calling reset or performing measurements
c. Using a single classical bit from a large register
d. Using barrier to separate broadcasts
answer
The answer is b.
Having reset or measurements inside conditionals is not supported in current Qiskit Runtime restrictions. The other actions are allowed (within normal constraints).
- What is the purpose of
qiskit.circuit.classical.exprin the context of dynamic circuits?
a. It optimizes quantum gate scheduling at transpile time
b. It represents runtime classical expressions (e.g., XOR parity) used in conditions
c. It converts OpenQASM 2 to Qiskit circuits
d. It provides arithmetic operations for classical ALU inside hardware
answer
The answer is b.
The expr module offers an exploratory representation for building runtime classical expressions (e.g., parity via XOR) that can be used with QuantumCircuit.if_test(). Arithmetic/ALU operations are not supported; only boolean logic in the supported conditions is available.
- Which statement best captures the current platform support as described in the guide?
a. All OpenQASM 3 control-flow features (for, while, if) are supported in Qiskit Runtime
b. Only if is supported in Qiskit Runtime; in Qiskit SDK this is exposed as QuantumCircuit.if_test
c. Qiskit Runtime supports if and while but not for
d. Qiskit SDK supports none of OpenQASM 3 control-flow features
answer
The answer is b.
Qiskit Runtime currently only supports the conditional if statement from OpenQASM 3. In Qiskit SDK this capability is exposed via the if_test context manager.
- In a job, you measure into
cr1(32 bits) andcr2(32 bits), then immediately test both registers in twoif_teststatements without a barrier. Why can this be invalid?
a. Two separate if_test blocks are illegal in the same circuit
b. The total broadcasted bits (32 + 32) can exceed the 60-bit limit in one broadcast group
c. Measuring more than 32 qubits in one job is not supported
d. The barrier instruction is deprecated in dynamic circuits
answer
The answer is b.
Broadcasting more than 60 bits at a time is not allowed. Testing both 32-bit registers back-to-back without separating broadcasts can exceed the 60-bit-per-broadcast limit; inserting a barrier() can split them into separate broadcasts and satisfy the constraint.
- Which statement about early access and performance trade-offs is accurate?
a. Dynamic circuits are GA and have no performance considerations
b. Mid-circuit measurement and classical ops can increase execution time compared to two-qubit gates
c. Mid-circuit measurement is always faster than two-qubit gates, reducing latency
d. Qiskit Runtime disallows any mid-circuit measurement entirely
answer
The answer is b.
Dynamic circuits are early access in Runtime and that mid-circuit measurements plus classical feedforward can lengthen execution time relative to two-qubit gates, potentially offsetting depth reductions.
- Which example use case is highlighted as benefiting from dynamic circuits?
a. Amplitude estimation via deep, fixed-depth circuits only
b. Efficient sampling of IQP-like circuits
c. Only classical simulation improvements
d. Transpile-time peephole optimizations
answer
The answer is b.
There are several use cases, including efficient sampling of IQP-like circuits, efficient long-range entanglement on a chip, and shallow-state preparation (e.g., GHZ, W, and MPS families).
- Regarding OpenQASM 3 and Qiskit Runtime interoperability, which statement is correct?
a. Any OpenQASM 3 program with classical operations can be run directly in Runtime
b. Only instructions loadable into Qiskit are supported when passing OpenQASM 3 as input to Runtime primitives
c. Qiskit Runtime natively executes arbitrary OpenQASM 3 classical arithmetic
d. OpenQASM 3 input bypasses all Runtime limitations listed in the guide
answer
The answer is b.
When OpenQASM 3 is used as the input format, only instructions that can be loaded into Qiskit are supported. Classical operations beyond what Qiskit can load are not supported; the OpenQASM 3 feature table determines compatibility.
- You need to build an n‑qubit GHZ state using dynamic circuits with parity-based corrections. Which approach matches the guide?
a. Use arithmetic addition over classical bits to compute parity
b. Use qiskit.circuit.classical.expr.bit_xor to compute parity and guard x with if_test(parity)
c. Post-select results after execution; dynamic circuits are not used
d. Use nested if_test to encode multiple parities
answer
The answer is b.
The guide shows constructing GHZ states by computing parity using expr.bit_xor over measured bits and using that expression within if_test to conditionally apply x corrections. Arithmetic operations and nested if_test are not supported.
TASK 3.3: Transpile and optimize circuits¶
- Which of the following lists the preset transpiler pipeline stages in the correct order?
a. layout → routing → translation → optimization → scheduling → init
b. init → layout → routing → translation → optimization → scheduling
c. init → routing → layout → translation → scheduling → optimization
d. layout → translation → routing → optimization → init → scheduling
answer
The answer is b.
The preset pipeline in Qiskit’s staged pass managers is ordered as: init → layout → routing → translation → optimization → scheduling.
The init stage handles early housekeeping (e.g., reducing multi-qubit ops to 1–2 qubits where needed), then layout selects a mapping from virtual to physical qubits, routing inserts SWAPs as required by hardware connectivity, translation compiles to the target basis gates, optimization reduces depth and cancels redundant operations, and scheduling (only when requested) inserts delays and accounts for timing.
- Which statement best describes the purpose of the init stage?
a. It always runs by default and performs hardware-aware scheduling.
b. It performs SWAP insertion to ensure two-qubit connectivity.
c. It primarily enables early, optional cleanups and translates gates acting on 3+ qubits into 1–2 qubit operations.
d. It decomposes circuits into the backend basis and cancels adjacent CNOT gates.
answer
The answer is c.
The init stage does very little by default, but it’s where you can insert early optimizations if desired. Since many downstream algorithms expect only single- and two-qubit operations, this stage also translates any operation acting on three or more qubits into 1–2 qubit gates.
- In the layout stage, which pass uses a subgraph isomorphism approach (VF2++) to find an ideal mapping of virtual to physical qubits?
a. SabreSwap
b. VF2Layout
c. DenseLayout
d. TrivialLayout
answer
The answer is b.
VF2Layout treats layout selection as a subgraph isomorphism problem and uses VF2++ to search for candidate layouts; if multiple candidates are found, a scoring heuristic picks the one with the lowest average error.
- Which statement about TrivialLayout in the layout stage is correct?
a. It is the only layout method used at all optimization levels.
b. It randomly permutes qubits to maximize entangling gate parallelism.
c. It maps qubits in circuit order and is used historically at optimization level 1 to try a perfect layout before other methods.
d. It is the default stochastic router for SWAP insertion.
answer
The answer is c.
TrivialLayout naively maps virtual qubits to identically numbered physical qubits and is (historically) tried at optimization level 1 to see if a perfect layout exists; otherwise, other layout heuristics (such as VF2Layout or SabreLayout) are used.
- Why can repeated runs of the same circuit produce a distribution of depths after routing?
a. Because routing is solved exactly and deterministically for each run.
b. Because the SabreSwap router is stochastic, so SWAP insertion can vary across runs.
c. Because translation to basis gates happens before layout.
d. Because scheduling always inserts the same delays.
answer
The answer is b.
Finding an optimal SWAP mapping is NP-hard, so Qiskit uses the stochastic heuristic SabreSwap. Its randomness leads to different SWAP patterns on different runs, yielding a distribution of circuit depths and gate counts.
- In the translation stage, which of the following is true when the SWAP gate is not native to the backend?
a. It is executed directly as a hardware-native delay instruction.
b. It is decomposed into three CX gates (plus any necessary single-qubit gates).
c. It is replaced by a Toffoli (CCX) gate pair.
d. It is removed because SWAPs are never required on hardware.
answer
The answer is b.
When SWAP is not native to the target’s basis, it is decomposed into a sequence of native gates—commonly three CNOT (CX) gates—making SWAPs expensive on noisy hardware and motivating layout/routing that minimizes their use.
- Which preset optimization level includes passes such as Collect2qBlocks, ConsolidateBlocks, and UnitarySynthesis?
a. Level 0
b. Level 1
c. Level 2
d. Level 3
answer
The answer is d.
At optimization level 3, the staged pass manager adds deeper structural optimizations such as Collect2qBlocks, ConsolidateBlocks, and UnitarySynthesis, in addition to single-qubit optimizations and commutation-based cancellations.
- Which statement about the scheduling stage is correct?
a. Scheduling always runs by default after optimization.
b. Scheduling must be explicitly requested (e.g., via scheduling_method), and it inserts Delay instructions to account for idle times.
c. Scheduling is the stage that performs VF2 layout search.
d. Scheduling translates to the target basis and cancels adjacent CNOTs.
answer
The answer is b.
Scheduling does not run by default; you trigger it by specifying a scheduling_method (e.g., "asap"). It analyzes timing and inserts Delay instructions for idle periods, helping estimate execution timing on the backend.
- What is the recommended way to transpile a circuit in Qiskit?
a. Call transpile(circuit) only; pass managers are deprecated.
b. Create a preset staged pass manager with generate_preset_pass_manager(...) and call run(circuit).
c. Directly construct a StagedPassManager is forbidden; only PassManager is allowed.
d. Only schedule the circuit; layout and routing are optional and unnecessary.
answer
The answer is b.
The recommended workflow is to build a preset staged pass manager with generate_preset_pass_manager (choosing an optimization_level, backend, and options) and then invoke its run method on the circuit.
- Which description best characterizes a staged pass manager?
a. A pass manager composed directly of gates instead of passes.
b. A pass manager that contains one monolithic pass implementing all stages.
c. An abstraction that is composed of multiple pass managers, each representing a transpiler stage (e.g., layout, routing, translation).
d. A pass manager that only schedules circuits and cannot do layout or routing.
answer
The answer is c.
A StagedPassManager is built from per-stage PassManager instances (e.g., for layout, routing, translation), providing a higher-level abstraction aligned with the logical stages of transpilation.
- You start from a preset staged pass manager at optimization level 3 and want to add extra logical optimization before layout. What is a supported approach?
a. You cannot modify a preset pass manager.
b. Assign a custom pre_layout stage (e.g., an InverseCancellation pass list) to the staged pass manager.
c. Replace the router with generate_embed_passmanager, which is strictly for scheduling.
d. Insert scheduling analysis passes into the translation stage by default.
answer
The answer is b.
You can augment a preset staged pass manager by adding custom stages like pre_layout (e.g., with InverseCancellation) or by swapping out stages. Stage generator helpers such as generate_embed_passmanager can assist when building custom stages.
- Which statement about
transpilevs. preset staged pass managers is accurate?
a. transpile does not use pass managers internally.
b. transpile internally calls generate_preset_pass_manager and runs it on the circuit.
c. transpile always performs scheduling by default.
d. transpile can only accept lists of circuits, not a single circuit.
answer
The answer is b.
The simpler transpile function internally creates a preset staged pass manager via generate_preset_pass_manager using the given options (e.g., optimization_level) and then runs it on the input circuit(s).